Physical Design

Advanced Process Design

SEMIFIVE has accumulated extensive experience in advanced process technologies. Being the first Samsung Foundry’s DSP to design an SoC based on the the foundry’s 5nm process for their customer, SEMIFIVE has been enabling its customers to take advantages from leading FinFET process nodes such as Samsung Foundry’s 5nm, 8nm, 14nm and more. Through such experience, we work with our customers to explore design options and develop the best solution to meet each of their specific application’s requirements.

Design Expertise in Various Applications

Purpose-built custom chips create value by focusing on specific applications. In other words, the value can be maximized when every aspect of design is tailored and optimized for the target application. This is why design experience across various applications is essential in SoC designs today. Physical Engineering team members at SEMIFIVE have wide experience designs covering AI, LTE/5G, Vision/Camera, Digital TV, Mobile, AIoT and Automotive end markets. Meet the exact experience for the success of your next chip with SEMIFIVE.

Our Physical Design Capabilities

  • Place and Route in advanced FinFET nodes (14nm/8nm/5nm and more)
    • Tapeout experiences in Samsung Foundry 5nm
    • Experienced Complex Power Domains with UPF
  • Parasitic Extraction with StarRC
  • Physical Verification Signoff with ICV and Calibre
  • IR/EM/Jitter signoff with Redhawk and Redhawk-SC
  • Timing ECO and signoff with PrimeTime
  • Physical Synthesis/SCAN/BIST
  • Low power implementation and signoff
  • Full-Chip SoC tapeout

Examples of Design Projects


  • Technology:  Samsung 5nm
  • Application: Data Center AI SoC
  • Die Size: 11mm x 11mm
  • Operating Frequency:  1.5GHz for logic
  • Hierarchical Design
  • Main IPs
    • NE IP: 1.5GHz
    • Processor IP:  CA53 Quad (1.5GHz in ND)
    • Interface IP: DDR6, PCIe Gen5
    • FlexNOC Bus
  • Responsibilities
    • Hierarchical P&R (full-chip)
    • RDL routing and BUMP
  • Power/Signal EM, IR, DVD signoff (full-chip)Physical Verification Signoff (full-chip)


  • Technology:  Samsung 14nm
  • Application : Data Center AI SoC
  • Die Size: 14mm x 13mm
  • Operating Frequency :  2GHz
  • Hierarchical Design
    • Physical Partitions: 23 ea
    • Instance Count: 90M
  • Main IPs
    • Processor IP:  RISC-V U74-MC, Customer IP (2GHz in OD)
    • Interface IP: LPDDR4 (4.267GHz), PCIe Gen4
  • Responsibilities
    • Hierarchical P&R (full-chip)
    • RDL routing and BUMP
    • Power/Signal EM, IR, DVD signoff (full-chip)
    • Physical Verification Signoff (full-chip)

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