Job Purpose
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Principal Accountabilities
1. Floorplan
2. Powerplan
3. Place & optimization
4. CTS (clock tree synthesis)
5. Optimization before routing
6. Routing
7. Route optimization
8. GDS out
Qualifications
1. Automatic P&R (place and route) 을 수행하기 위한 EDA software의 이해
• SW 종류: ICC2, Innovus, Calibre, ICV, StarRC 5
2. P&R flow에 대한 각 단계의 개념 이해
3. EDA SW들에 대한 사용 경험 우선
4. TCL (tool command language) 경험 우선
5. 반도체 (ASIC/SOC) 설계 관련 과목 수강 경험 우선
6. Verilog HDL 언어에 대한 경험
공통 요건
• 4년제 대졸 이상
• 석사 우대
• 컴퓨터공학, 소프트웨어학, 전자공학 및 반도체 관련 학과 혹은 관련 교육을 받은 자
About SEMIFIVE
Founded in Seoul in 2018, SEMIFIVE is basing its foundation on Korea’s semiconductor design competency that was amassed for more than 20 years. With expertise in front-end to back-end design, SEMIFIVE has become the fastest-growing silicon design company that offers the most comprehensive design solutions. SEMIFIVE’s core business is its innovative Platform SoC that enables low-cost & high-efficiency SoC design, and also provides various design solutions for global customers through its diverse network. As the cost of developing an SoC and the demand for customized silicon continue to grow rapidly, SEMIFIVE’s Platform SoC will play a key role in turning innovative ideas into silicon.
SEMIFIVE, hand in hand with global innovation leaders, is growing as a leading partner for future SoC designs, and thereby becoming: The New Global Hub of Custom Silicon.