PMO

• SoC Development PM (Project Management)

  As an SoC Development PM, you are responsible for project management of SoC development project, which covers each development work (SoC architecture, logic design & verification, physical implementation (synthesis, DFT, STA), package design, ATE test, chip validation, and qualification) and development plan (schedule, engineering resources, risk management)

  Principal Accountabilities

  • Define a project plan (schedule, engineering resources, risk management) with related function team leads
  • Organize each function team to execute an SoC development project
  • Review project progress/status and define action items to fix issues/problems
  • Identify risk items and make an execution plan to hedge the risks
  • Collect the customer’s voice/feedback and provide a solution for customers to be fully satisfied
  • Use SW tools to systematically manage the project
  • Define a key success factor and its target for the project

  Key Performance Measures

  • The project to be executed on time as planned (meet the major milestone timelines)
  • Issues and risks to brought up earlier and to be fixed with reasonable efforts
  • Each function team to be collaborated with a productive and proactive manner
  • The customer to be satisfied with good communication and information sharing

  Qualifications

  • Experience and knowledge on SoC development covering logic design and/or physical design
  • Knowledge and understanding on semiconductor device and its manufactuing
  • Experience to lead an SoC development project as a project lead or a PM (plus factor)
  • Fluency in English (plus factor if graguated in English speaking country for high school or Bachelor/Master/Ph.D. degrees)
  • Minimum of 18 years experience in related field or 12 years experience with fluent English
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form

• Application Engineer

  As an Application Engineering Manager, you are responsible for validating chip functionality while working closely with logic, software, and hardware engineers

  Principal Accountabilities

  • Perform chip validation while manupulating evaluation board and test equipments
  • Peform debugging to find a root cause for malfunction and no-function cases
  • Guide and support all aspects of chip validation
  • Test and debug technical issues in evaluation board, application board, FPGA board
  • Analyzes possible solutions using standard procedures
  • Ensure complete and accurate test report generation
  • Develop and maintain good technical understanding and knowledge in area of expertise
  • Perform local field tests of reference design as needed

  Key Performance Measures

  • Skill to validate chip functionality with test equipment and embedded programming
  • Understanding SoC architecture, mega IPs and peripheral functions
  • Strong logical and creative problem-solving skills

  Qualifications

  • Minimum of 7 years in related field
  • Good applied knowledge of measuring techniques and instruments
  • Experience with device drivers and understanding of hardware devices
  • Good understanding of chip validation process
  • Experiences in DDR/LPDDR or PCIe verification is preferred
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

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Engineering

• Senior PCIe Engineer

  As an Engineer, you will participate in the definition, design, implementation, and verification of all parts of PCIe.

  Principal Accountabilities

  • Perform board electrical and mechanical simulation and check across specification and requirements
  • Guide and support all aspects of PCB layout, fabrication and assembly processes
  • Drive PCB and Board outsourcing
  • Design and Verification of PCIe IPs
  • PCIe bring up

  Key Performance Measures

  • Understanding PCIe architecture and Bus architecture
  • Skill for understanding the board schematic and PCB layout
  • Will and action to break down the repetitive or routine tasks

  Qualifications

  • BSEE, BSCE, BSCS, or related degree
  • 5 years of experience in hardware and/or applications engineering or related role (or 3 years of experience will be considered if you have a MSEE/MSCE or related degree)
  • Experience with RTL design in Verilog and/or SystemVerilog
  • Experience with PCIe and/or coherent protocols such as UPI
  • Experience with PCIe driver
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form

• Senior Memory Controller Engineer

  As an Engineer, you will participate in the definition, implementation, and verification of all parts of Memory Controller.

  Principal Accountabilities

  • Perform board electrical and mechanical simulation and check across specification and requirements
  • Guide and support all aspects of PCB layout, fabrication and assembly processes
  • Drive PCB and Board outsourcing
  • Design and Verification of Memory Controller IPs
  • DDR/LPDDR high-speed memory bring up

  Key Performance Measures

  • Understanding Memory Controller and PHY architecture and Bus architecture
  • Skill for understanding the board schematic and PCB layout
  • Will and action to break down the repetitive or routine tasks

  Qualifications

  • BSEE, BSCE, BSCS, or related degree
  • 5 years of experience in hardware and/or applications engineering or related role (or 3 years of experience will be considered if you have a MSEE/MSCE or related degree)
  • Experience with RTL design in Verilog and/or SystemVerilog
  • Experience with Memory Controller and/or coherent protocols
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form

• IP/SoC Verification Engineer

  As a Verification Engineer on the Logic Design team, you will participate in the definition, implementation, and execution of our verification strategy, as well as being a key participant in the analysis of our IP/SoC verification quality of results. This position is a highly visible role, the simple purpose of which is to ensure the silicon works. By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of supported instruction set and with various peripherals and bus interconnect architectures. Implementing design verification methodologies that can accommodate such variation is a challenging task, to be addressed in this role.

  Principal Accountabilities

  • Architect test methodologies applicable to a wide range of processor and IP/SoC designs
  • Perform initial debug of test failures to identify design errors
  • Collaborate closely with the design team to address any design errors
  • Understand custom microprocessor and SoC designs from an architectural level, and use this understanding to envision effective verification strategies for these designs
  • Create a test plan to codify this strategy, taking account of such issues as design feature priority, potential customer impact, coverage metrics generation and measurability, etc.
  • Create test suites (UVM, C, or otherwise, as needed) to execute this strategy
  • Drive the execution of these test suites (scripting, Makefiles, etc.)
  • Analysis of test results, including RTL or higher-level debug of test failures
  • Interact with the design team to help drive bug closure

  Key Performance Measures

  • Understanding SoC architecture and Bus architecture
  • Skill for handling scripts, OOP high level languages, data structure, algorithms and so on
  • Will and action to break down the repetitive or routine tasks

  Qualifications

  • A minimum of 3 years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, Verilog, Makefiles, scripting languages, etc.). Especially in hands-on testbench and test suite generation
  • A conscientious and thorough approach to Design Verification - Attention to detail. Thoroughness is essential in this role
  • Solid understanding of processor, SoC architecture, Bus architecture (ex. AMBA, Tilelink), or a strong desire and ability to learn same
  • A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, code coverage, iteration until coverage closure)
  • Ability to effectively assess the current state of a design’s verification posture, remaining state space to be covered, and efficient methods to achieve verification closure
  • Knowledge of Verilog/System Verilog, digital simulation and debug with various verification tools (VCS, Xcelium, Questa, Verdi, etc)
  • Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.)
  • Ph.D or Master’s degree in Electrical Engineering, Computer architecture, or Computer Science is a plus
  • Experience of Static Verification tools is a plus
  • Ability to work with team playing based on opensource environment is a plus (ex. using Github)
  • Experience with Perl, Python or similar scripting language is a plus
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form

• Junior/Senior Physical Design Engineer

  AAs a Physical Design Engineer on the Physical Design team, you will participate in the synthesis, floorplan, clock tree synthesis, power distribution, I/O planning and hard IP integration, timing closure and physical verification.

  Principal Accountabilities

  • Physical Synthesis
  • Floorplan including Multi-level hierarchical design
  • Clock Tree Synthesis
  • Power Planning and Distribution
  • Place and routing
  • Static Timing Analysis and Timing Closure
  • Physicla Verification : DRC, LVS
  • Power Analysis : StaticIR Drop & Dynamic Voltage Drop Analysis, Power & Signal EM Analysis

  Key Performance Measures

  • Work with logic design team and physical implementation team to understand partition architecture and drive physical aspects early in design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Timing, physical verification, driving the signoff closure for the partitions. Resolve design and flow issues related to physical design, identify potential solutions and drive execution.

  Qualifications

  Senior Physical Designer Engineer
  • 4년제 대졸이상, 석사 우대
  • Chip Top 경험자 우대: Hierarchy Design 경험 (Over 10 Blocks) , Block Partition, Top CTS
  • CPU/GPU Hardening 경험자 우대
  • P&R Experience: Floorplan, Place & Route, CTS, STA, DRC/LVS, IR Drop (ICC or Innovus, Prime-Time, StarRC, ICV or Calibre, RedHawk)
  • TSMC 16nm/12nm or Samsung 14nm 이하 경험자 우대
  
  Junior Physical Designer Engineer
  • 4년제 대졸이상, 석사 우대
  • 전기/전자/컴퓨터 공학 관련 전공
  • Digital Logic, Computer Architecture, VLSI, 반도체 관련 과목 이수
  • Synopsys/Cadence EDA Tool 사용 경험자 및 교육 이수 자 우대.
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form

• SoC Physical Implementation Engineer

  As a Physical Implementation Engineer, you will participate in the synthesis, SDC Clean(GCA), Eauivalence check, DFT(BIST/BIRA/SCAN) Design&verification, UPF low power design and Static Timing Analysis(Timing Closure).

  Principal Accountabilities

  • DFT Implementation
  
    - SCAN insertion / ATPG / Scan Simulation (Test Compiler / TetraMax)
  
    - BIST/BIRA Insertion & Simulation : Tessent MBIST / JTAG / IJTAG
  
    - SDC Creation & Clean
  
    - Spyglass LINT/SDC/DFT Check
  
    - Logic Synthesis : DC/DCT/DCG
  
    - Equivalence Check : Formality/Conformal
  
    - LDRC : Logic Design Rule Check (Spyglass_LDRC)
  
    - Timing Closure : cross-talk/noise/mttv/setup/hold fix (Prime_Time, Physical-aware ECO)
  
    - Low Power Design : UPF Creation & Low power Rule Check(VC_LP)
  
    - Multi-voltage, Multi power domain, Power-gating, Clock-gating.
  
    - Power Analysis : Vectored / Vectorless (PTPX)
  
    - Implementation 자동화Platform 개발
  
  
  • Simulator & Debugger : VCS / NC-verilog / Verdi

  Key Performance Measures

  • Understanding SoC/ASIC design flow.
  • Perform Hierarchical Implementation(SYN/DFT/STA/UPF) in Samsung 14nm or less process.

  Qualifications

  • Scripting (shell, tcl, perl, phython, etc.) 능력 보유
  • Version Control system (Git, CVS, ClearCase, Perforce, etc.) 사용 가능
  • Bus protocol (AMBA, NoC 등) 이해
  • 영어 능통 (어학 자격 소지, Business letter/email reading & writing 가능, etc.)
  
  [우대 사항]
  
  1. 신입
  • 전기/전자/컴퓨터공학 관련 전공
  • 자료구조, 알고리즘 관련 과목 이수 및 우수 성적
  • 디지털 논리 회로, 컴퓨터 구조론 관련 과목 이수 및 우수 성적
  • VLSI/반도체 관련 과목 이수 및 우수 성적
  • EDA tool 교육 이수
  
  2. 경력
  • DFT 전문성 보유
    - Top level DFT Architecture 설계 경험자
  
    - HPDF DFT 경험자 (Top/Block level)
  
    - ATE Vector setup 및 Yield 개선 업무 경험자
  
    - IJTAG(IEEE1687) 경험자 (Tessent tool 이용)
  
  
  • Hierarchical implementation Flow 경험자유
  • SEC 14nm 이하 공정 경험자
  • CPU (ARM Cortex Series, RISC-V 등) 1.0 GHz 이상 Hardening 경험
  • DVFS implementation 경험.
  • HSI IP Hardening 경험자 (LPDDR4 PHY / PCIe PHY / Ethernet PHY / SerDes PHY)
  • 설계 자동화 platform 개발 경험자
  • High-frequency Bus 구현 경험자
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form

• Firmware & Embedded Linux Engineer

  As an embedded software engineer, you will be responsible for writing device drivers for both Linux and bare metal applications which are running on our Custom Silicon.

  Principal Accountabilities

  • Architect and design Linux Device Drivers
  • Board bring up and test of embedded platforms
  • Develop or customize board support packages (BSP) for our hardware to provide the required functionality
  • Write device drivers for bootloaders and the Linux kernel
  • Design and implement software for embedded devices and systems from requirements to production and commercial deployment
  • Be an active participant in software architecture discussions

  Key Performance Measures

  • Solid knowledge of processor architecture, operating system concepts, and modern software development processes and best practices

  Qualifications

  • Proficient in C/C++ programming, and know how to use embedded development tools e.g. Trace32/J-Link/OpenOCD based JTAG debuggers.
  • Must have good knowledge of System software, Microprocessors/Microcontrollers, Memory subsystem, Hardware IPs
  • Must have experience to develop and debug linux device drivers
  • Experience with Linux kernel programming and OS internals
  • Work experience on ARM Cortex platforms (M0/M3/M4/ A7/A9/A53 etc.)/ MIPS/RISC-V cpus
  • Familiar with the common SoC peripheral drivers, such as UART, I2C, SPI, USB, SDIO, Ethernet, PCIe MIPI, Display Port, etc.
  • Proven experience in BSP, bootloader development
  • Strong ability to analyze, locate, solve problems, with teamwork and self-drive awareness
  • Familiarity with software configuration management tools e.g. git , defect tracking tools, and peer review
  • Increase efficiency through automation and application of appropriate scripting, tools, and innovation
  • Sense of ownership of complete module/task
  • Great interpersonal and communication skills
  
  [Advantages]
  • Contribution on Open Source community
  • Knowledge of HW - RTL(Verilog)
  • Customer Support Experience
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form

CTO Office

• SoC System Controller Principal

  Platform SoC 용 System Controller의 완성도/경쟁력 확보를 위해 28nm ~ 3nm SoC의 System Controller 구조 및 H/W적 필요 요소의 정리와 확보.

  Principal Accountabilities

  • Consumer/Computing/Edge/Industrial/Automotive 등 주요 SoC Application 별 필요한 SoC 구성 요소 이해를 기반으로 Platform SoC에 필요한 System Controller IP 정의
  • SoC 주요 Component를 Integration하기 위해 기본 회로로서 Test/Reset/Clock/Booting/Security/Basic Periphera (INTC/DMA/Timer, UART, SPI 등)의 주요 Requirement 정리
  • 주요 System Controller IP의 기능/성능 Benchmark
  • System Controller IP의 S/W Programming Model 정의
  • System Controller Technical Documentation
  • System Controller IP의 자체개발 협력, 외부 도입 등 필요 IP 확보

  Key Performance Measures

  • Platform SoC 용 System Controller Definition 산출물과 경쟁력
  • Platform SoC 과제 일정에 맞는 On-time Delivery
  • H/W, S/W 개발팀과 협력

  Qualifications

  • System Controller의 기능적 특성, 역할, 핵실 설계 포인트 이해 수준
  • SoC 설계, 검증, Fabrication, Test 등 SoC 설계 및 양산 과정 전반에 대한 이해 수준
  • Low-power Design Methodology 이해
  • SoC System Controller 설계 참여 경력 (3개 이상의 SoC 설계 경험)
  • HDL, Programming Language 작성 능력
  • Communication Skill 및 영어 능력
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form

• SoC Computing Cluster Principal

  Application 및 고객의 요구에 부합하는 SoC의 Computing Cluster (CPU Cores, L2-/L3-Cache, & GPU)의 구성 도출, Coremark과 같은 Benchmark S/W의 예상 스코어 예측, Integration Guide 제시

  Principal Accountabilities

  • Consumer/Computing/Edge/Industrial/Automotive 등 주요 SoC Application에 따라 필요한 SoC 용 Computing Cluster의 구성 도출 (CPU Core Configuration, L2-/L3-Cache 종류 및 Size, GPU Configuration)
  • SoC Computing Cluster Performance Modeling 및 Benchmark Score 예측
  • Computing Cluster를 위한 Programming Model 제시
  • Computing Cluster의 SoC-level Verification Guide
  • Computing Cluster Technical Documentation
  • Computing Cluster Core의 자체개발 협력, 외부 도입 등 필요 Core 확보

  Key Performance Measures

  • Platform SoC 용 Computing Cluster 구조 경쟁력, Benchmark Score 예측 정확성 (예측 vs. 실측)
  • Platform SoC 과제 일정에 맞는 On-time Delivery
  • H/W, S/W 개발팀과 협력

  Qualifications

  • Computing Cluster 구성 요소 및 Requirement 이해, 경쟁 기술의 이해
  • SoC 설계, 검증, Fabrication, Test 등 SoC 설계 및 양산 과정 전반에 대한 이해 수준
  • Benchmark의 이해, Low-power Design Methodology 이해
  • SoC Computing Cluster 설계 참여 경력 (3개 이상의 SoC 설계 경험)
  • HDL, Programming Language 작성 능력
  • Communication Skill 및 영어 능력
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form

• SoC NOC/Memory Subsystem Principal

  Application 및 고객의 요구에 부합하는 SoC의 NOC (i.e. On-chip Bus), Memory Subsystem 확보, System BW & Memory Subsystem BW 예측, Integration Guide 제시

  Principal Accountabilities

  • Consumer/Computing/Edge/Industrial/Automotive 등 주요 SoC Application에 따라 필요한 SoC 용 NOC, Memory Subsystem (DRAM, Flash) 구성 도출
  • SoC 용 NOC, Memory Subsystem BW & Utilization 예측
  • NOC, Memory Subsystem을 위한 Performance Model 제시
  • NOC, Memory Subsystem의 SoC-level Verification Guide
  • NOC, Memory Subsystem Technical Documentation
  • NOC, Memory Subsystem의 자체개발 협력, 외부 도입 등 필요 IP 확보

  Key Performance Measures

  • Platform SoC 용 NOC, Memory Subsystem 경쟁력, Performance 예측 정확성 (예측 vs. 실측)
  • Platform SoC 과제 일정에 맞는 On-time Delivery
  • H/W, S/W 개발팀과 협력

  Qualifications

  • NOC, Memory Subsystem 구성 요소 및 Requirement 이해, 경쟁 기술/표준의 이해
  • SoC 설계, 검증, Fabrication, Test 등 SoC 설계 및 양산 과정 전반에 대한 이해 수준
  • Performance Profiling의 이해, Low-power Design Methodology 이해
  • NOC, Memory Subsystem 설계 참여 경력 (3개 이상의 SoC 설계 경험)
  • HDL, Programming Language 작성 능력
  • Communication Skill 및 영어 능력
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form

• SoC External Bus Interface Principal

  Application 및 고객의 요구에 부합하는 SoC 용 External I/F IP 확보 (USB, PCIe, Ethernet), IP 경쟁력 분석 (기능/성능), Integration Guide 제시

  Principal Accountabilities

  • Consumer/Computing/Edge/Industrial/Automotive 등 주요 SoC Application에 따라 필요한 SoC 용 External I/F IP (USB, PCIe, Ethernet) 구성 도출
  • SoC 용 External I/F IP (USB, PCIe, Ethernet) 상세 사양 정의. 실효 성능 예측
  • External I/F IP (USB, PCIe, Ethernet)를 위한 Programming Model 제시
  • External I/F IP (USB, PCIe, Ethernet)의 SoC-level Verification Guide
  • External I/F IP (USB, PCIe, Ethernet) Technical Documentation
  • External I/F IP (USB, PCIe, Ethernet)의 자체개발 협력, 외부 도입 등 필요 IP 확보

  Key Performance Measures

  • Platform SoC 용 External I/F IP (USB, PCIe, Ethernet) 경쟁력, Performance 예측 정확성 (예측 vs. 실측)
  • Platform SoC 과제 일정에 맞는 On-time Delivery
  • H/W, S/W 개발팀과 협력

  Qualifications

  • External I/F IP (USB, PCIe, Ethernet) 구성 요소 및 Requirement 이해, 경쟁 기술/표준의 이해
  • SoC 설계, 검증, Fabrication, Test 등 SoC 설계 및 양산 과정 전반에 대한 이해 수준
  • Performance Profiling의 이해, Low-power Design Methodology 이해
  • External I/F IP (USB, PCIe, Ethernet) SoC Integration 경력 (3개 이상의 SoC 설계 경험)
  • HDL, Programming Language 작성 능력
  • Communication Skill 및 영어 능력
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form

• SoC NPU Principal

  Application 및 고객의 요구에 부합하는 SoC 용 NPU (Neural Processing Unit) 필요사양 정의 및 경쟁력 분석과 Core 확보, Integration Guide 제시

  Principal Accountabilities

  • Consumer/Computing/Edge/Industrial/Automotive 등 주요 SoC Application에 따라 필요한 SoC 용 NPU 사양 도출
  • SoC 용 NPU Core 상세 기능, 지원 Network 정의, 예상 실효 처리 성능 예측
  • NPU활용을 위한 Programming Model 제시
  • NPU의 SoC-level Verification Guide
  • NPU의 Technical Documentation
  • NPU의 자체 개발 협력 및 외부 도입 등 필요 IP 확보

  Key Performance Measures

  • Platform SoC 용 NPU Core 경쟁력, Performance 예측 정확성 (예측 vs. 실측)
  • Platform SoC 과제 일정에 맞는 On-time Delivery
  • H/W, S/W 개발팀과 협력

  Qualifications

  • Deep Learning 및 DNN H/W Acceleration의 이해, 주요 DNN의 특징과 용도 이해
  • SoC 설계, 검증, Fabrication, Test 등 SoC 설계 및 양산 과정 전반에 대한 이해 수준
  • Performance Profiling의 이해, Low-power Design Methodology 이해
  • NPU Core 개발 또는 SoC Integration 경력, 일반 SoC 개발 경험 (3개 이상의 SoC 설계 경험)
  • HDL, Programming Language 작성 능력
  • Communication Skill 및 영어 능력
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

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• Advanced High-level SoC Designer (With High-level H/W Construction Language)

  Front-End 설계 효율화를 위해 강력하고 다양한 설계자동화 방법론을 도입하고 있는SEMIFIVE에서 설계방법론의 창의적인 혁신과 개발 담당

  Principal Accountabilities

  • General understandings on computer architecture, operating systems, VLSI design, digital logic design, & semiconductor manufacturing
  • Programming skills (either one or all): C/C++, Python, Java
  • Digital Logic design skills – Verilog-HDL, Digital-logic Testbench, simulation & debugging
  • Design Automation – Concepts, Tools, Design-flow
  • Experiences in SoC Architecture – SoC Design Components, Design Constraints, Clock/Power-design, Test Logics, Full-chip Verification, Booting Mechanism, Programming Model, Resource Allocation/Maps, Off-chip Interface
  • SoC Top-level Integration (2+ SoC designs)

  Key Performance Measures

  • Tool 개발 진척도
  • 개발 Tool의 SoC 과제 적용 수준
  • 조직 내 개발 협력 기여

  Qualifications

  • 전산/전자/컴퓨터공학 관련 전공
  • SoC 설계 경험 (Digital 설계, 검증, DFT)
  • 14 nm SoC 또는 이후의 Advanced Node 개발 경험
  • Script Language (Tcl, Perl, or Python) 활용 중급 이상
  • Code Control system (Git, CVS, ClearCase, Perforce, etc.) 사용 경험
  • 영어 구사 가능 (영어 회의 가능, 어학 자격 소지, Business letter/email reading & writing 가능)

  Key Relationships

  • Open S/W 개발자
  • 사내 개발팀
  
  
  

  Send your resume to SEMIFIVE HR [ hr@semifive.com ]

  [Download] application form