{"id":4750,"date":"2022-04-28T23:17:02","date_gmt":"2022-04-28T14:17:02","guid":{"rendered":"https:\/\/semifive.com\/technology\/logic-design\/"},"modified":"2026-04-16T15:50:42","modified_gmt":"2026-04-16T06:50:42","slug":"logic-design","status":"publish","type":"page","link":"https:\/\/semifive.com\/ko\/technology\/logic-design\/","title":{"rendered":"Logic Design"},"content":{"rendered":"\n
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Technology<\/h4>\n\n\n\n

Logic Design<\/h1>\n<\/div>\n<\/div><\/div>\n<\/div>\n<\/div>\n\n\n\n
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SoC \uc544\ud0a4\ud14d\ucc98<\/h2>\n\n\n\n

\uc560\ud50c\ub9ac\ucf00\uc774\uc158 \uc694\uad6c \uc0ac\ud56d\uc744 \ucda9\uc871\ud558\ub294 SoC \uc0ac\uc591\uc744 \uacb0\uc815\ud558\uace0 \uc774\ub97c \uad6c\ud604\ud558\ub294 SoC \uc544\ud0a4\ud14d\ucc98\ub97c \uc124\uacc4\ud558\ub294 \uac83\uc740 SoC \uc124\uacc4\uc5d0 \uc788\uc5b4 \ucd5c\ub300 \ub09c\uc81c\ub77c\uace0 \ud560 \uc218 \uc788\uc2b5\ub2c8\ub2e4. \uc774\ub97c \ud574\uacb0\ud558\uae30 \uc704\ud574 SEMIFIVE\uc758 \uc544\ud0a4\ud14d\ucc98 \uadf8\ub8f9\uc740 \ub2e4\uc74c\uacfc \uac19\uc740 \ub0b4\uc6a9\uc744 \uc81c\uacf5\ud569\ub2c8\ub2e4.<\/p>\n\n\n\n

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  • Design Exploration based on Platform Architecture\n
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    • Analyze domain\u2013specific SoC requirements<\/li>\n\n\n\n
    • Provides SoC architecture based on the analysis <\/li>\n<\/ul>\n<\/li>\n\n\n\n
    • Architecture Implementation and Optimization\n
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      • RISC-V, ARM (with multicore implementation)<\/li>\n\n\n\n
      • Tilelink, AMBA (PL301, NIC400, MMU400)<\/li>\n\n\n\n
      • WorldGuard, TrustZone<\/li>\n\n\n\n
      • Physical aware subsystem design<\/li>\n\n\n\n
      • Parameterized design (Chisel based)<\/li>\n<\/ul>\n<\/li>\n\n\n\n
      • System Integration\n
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        • Reset, Clock, Power<\/li>\n\n\n\n
        • Design Automation<\/li>\n\n\n\n
        • Document Generation<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/div>\n\n\n\n
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          \"\"<\/figure>\n<\/div>\n<\/div>\n\n\n\n\n
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          SoC \uac80\uc99d<\/h2>\n\n\n\n

          \ubcf5\uc7a1\ud55c SoC \uc124\uacc4\uc758 \uc131\uacf5 \uc5ec\ubd80\ub97c \uacb0\uc815\ud558\ub294 \uac83\uc740 \ud6a8\uc728\uc801\uc774\uace0 \uc815\ud655\ud55c \uac80\uc99d \ud504\ub808\uc784\uc6cc\ud06c\uc785\ub2c8\ub2e4.
          SEMIFIVE\ub294 \ud0c4\ud0c4\ud55c SoC \uc124\uacc4 \ubc0f \uc2e0\uc18d\ud55c \uac1c\ubc1c\uc774 \uac00\ub2a5\ud558\ub3c4\ub85d \uc720\uc5f0\ud558\uace0 \uc644\uc804\ud55c \uac80\uc99d \ud504\ub808\uc784\uc6cc\ud06c\ub97c \uc81c\uacf5\ud569\ub2c8\ub2e4.<\/p>\n\n\n\n

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          FPGA \ud504\ub85c\ud1a0\ud0c0\uc774\ud551<\/h2>\n\n\n\n

          FPGA\ub294 \uc124\uacc4 \uac80\uc99d, \uc18c\ud504\ud2b8\uc6e8\uc5b4 \uacf5\ub3d9 \uac1c\ubc1c \ub4f1\uc5d0 \uc0c1\ub2f9\ud55c \uc774\uc810\uc744 \uac00\uc838\ub2e4\uc904 \uc218 \uc788\uc9c0\ub9cc, \ub300\uaddc\ubaa8\uc758 \ubcf5\uc7a1\ud55c SoC \uc124\uacc4\uc5d0\uc11c \uc774\ub7ec\ud55c \uc774\uc810\uc744 \uc5bb\uc73c\ub824\uba74 \uad11\ubc94\uc704\ud55c \uc804\ubb38 \uc9c0\uc2dd\uc774 \ud544\uc694\ud569\ub2c8\ub2e4.
          SEMIFIVE\ub294 \uc774\ub7ec\ud55c \uc774\uc810\ub4e4\uc744 \uc27d\uac8c \uc2e4\ud604\ud560 \uc218 \uc788\ub3c4\ub85d \ud544\uc218\uc801\uc778 \uc18c\ud504\ud2b8\uc6e8\uc5b4 \uc9c0\uc6d0\uc774 \ud3ec\ud568\ub41c FPGA \ud50c\ub7ab\ud3fc\uc744 \uc81c\uacf5\ud569\ub2c8\ub2e4.<\/p>\n\n\n\n

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          FPGA \uad6c\ud604<\/h3>\n\n\n\n
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          • Advanced Synthesis using FPGA tool (Vivado)<\/li>\n\n\n\n
          • Run DRC Check and Compilation Units in FPGA Synthesis tool<\/li>\n<\/ul>\n<\/div>\n\n\n\n
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            FPGA \uac80\uc99d<\/h3>\n\n\n\n
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            • Verify core and peripherals functions with FPGA board<\/li>\n\n\n\n
            • Test FPGA board for Development of device driver or porting OS<\/li>\n<\/ul>\n<\/div>\n<\/div>\n\n\n\n
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              FPGA \ud50c\ub7ab\ud3fc \ud558\ub4dc\uc6e8\uc5b4<\/h3>\n\n\n\n
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              HAPS-100 \uc2dc\uc2a4\ud15c<\/h4>\n\n\n\n
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              • FPGA: Xilinx UltraScale+ VU19P x 4ea<\/li>\n\n\n\n
              • PCI Express Lane: x4<\/li>\n\n\n\n
              • PCI Express Link Speed: 2.5GT\/s to 16GT\/s<\/li>\n\n\n\n
              • DDR4: DIMM 8GiB Micron<\/li>\n\n\n\n
              • Serial Flash<\/li>\n\n\n\n
              • JTAG & GPIO<\/li>\n<\/ul>\n<\/div>\n\n\n\n
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                VCU118 \uc2dc\uc2a4\ud15c<\/h4>\n\n\n\n
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                • FPGA: Xilinx UltraScale+ VU9P x 1ea<\/li>\n\n\n\n
                • PCI Express Lane: Gen3 x 16<\/li>\n\n\n\n
                • DDR4: Dual 80bit<\/li>\n\n\n\n
                • JTAG & GPIO<\/li>\n<\/ul>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n
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                  \ucd94\uac00 \uc815\ubcf4 \uc5bb\uae30<\/h2>\n\n\n