As a Physical Implementation Engineer, you will participate in the physical synthesis, physical verification, low power design(UPF) and Static Timing Analysis(Timing Closure).
- Physical synthesis
– Multi hierarchy design flow
– SDC understand & modification
– Compicated clock tree synthesis
– STA (Static Timing Analysis)
– Timing Closure : cross-talk/noise/mttv/setup/hold fix (Prime_Time, Physical-aware ECO)
– Low Power Design : UPF understand & Low power Rule Check
– Multi-voltage, Multi power domain, Power-gating, Clock-gating.
– Power Analysis
– Implementation 자동화 Platform 개발
- Physical Verification
– Calibre, ICV
Key Performance Measures
- Understanding SoC/ASIC design flow.
- Perform Hierarchical Implementation(auto P&R/STA/UPF) in Samsung 5nm process.
- Scripting (shell, tcl, perl, etc.) 능력 보유
- Version Control system (Git, Perforce, etc.)
- Experienced Design
- Experienced Big chip implementation
Founded in Seoul in 2018, SEMIFIVE is basing its foundation on Korea's semiconductor design competency that was amassed for more than 20 years. With expertise in front-end to back-end design, SEMIFIVE has become the fastest-growing silicon design company that offers the most comprehensive design solutions. SEMIFIVE's core business is its innovative Platform SoC that enables low-cost & high-efficiency SoC design, and also provides various design solutions for global customers through its diverse network. As the cost of developing an SoC and the demand for customized silicon continue to grow rapidly, SEMIFIVE's Platform SoC will play a key role in turning innovative ideas into silicon.
SEMIFIVE, hand in hand with global innovation leaders, is growing as a leading partner for future SoC designs, and thereby becoming: The New Global Hub of Custom Silicon.